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STM32F746 timer generated trigger for ext. ADC

Question asked by Michael Schmid on Jun 12, 2018
Latest reply on Jun 13, 2018 by Michael Schmid

Dear STM32 timer specialists,

 

i have to design a board, where a STM32F746 must read a 16 bit/40MSample ADC, into internal or external (SD)RAM. The ADC data bus will be 32 bit wide with 20MHz clock. The memory interface is an other problem, but i have to generate 3 different trigger signal for the ADC (it is 1 trigger signal, for 3 different configurations, to read 1, 2 or 3 channels). I have attached the timing diagram from the ADC datasheet.

 

My problem is now the question: can the trigger signal be generated by the STM32F746 timers, or do i need external logic to generate them. If possible, i would prefer the STM32F746 internal timer, to save board space and cost. Further would it be great if the sync-to-external-ref-clock feature of the STM32 timer could be used. After reading the STM32F746 datasheet and the "STM32 timer cookbook", i think the following setup should work(ADC_triggerGen_STM32F746_3ch.png):

 

  • APB1/2 bus setup for 200MHz
  • TIM2 with the ETR2(sync in) and OUT_CH2(or PWM_CH2) as MCLK for the ADC
  • --- TIM2 should divide the APBx frequency divide by 5 to output 40MHz
  • Ether TIM6,7,8,10,11 or 13 to count to 13(8,5) to generate the signal for the 3 channel(2 channel, 1 channel) trigger
  • TIM1 configured as one pulse timer, triggered by the above TIM(6,7,8,10,11 or 13) and ouput on PWM_CH1.This one pulse generator is needed to create the trigger pulse according the timing diagram of the ADC, it must be min. 5ns and max. 12.5ns.
  • 3 hardware pins used (ETR2, OUT_CH2, PWM_CH1)

 

This setup should work just in hardware, without CPU load if possible (except the setup and switching between 1channel, 2 channel or 3 channel mode).

 

The timing restrictions in timing_3ch_detail.png:

tPER    min=25ns (MCLK period)

tMCLKH    typ=0.5tPER (MCLK high period )

tMCLKL    typ=0.5tPER (MCLK low period )

tMRVSR    min=3ns (MCLK rising to VSMP rising time)

tVSD    min=2ns (VSMP pulse high time)

tMFVSF    min=7ns (MCLK falling to VSMP falling time)

MRVSR    min=3ns (MCLK rising to VSMP rising time)

 

Would be great, if someone could confirm, that this hardware setup can generate the required timing. Or hint me on possible limitations of the used timers. Then i could finalize the hardware part.

 

Thank you in advance for your help.

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