I'm having a little confusion interpreting the STM8S reference and STM8S903 data sheet. The STM8S903 is the part with TIM5 and TIM6 instead of TIM2 and TIM4, and adds the advanced triggering mechanism that allows linking the timers via trigger signals.
I'm feeding TIM1 an external clock via TIM1-ETR, and using all four CAPCOM output channels to drive external pins. The advanced features of TIM1 work well for this, since it has those four external channel pins and the ability to use an external pin as the clock source.
There is also a comment in the STM8S reference (§17.4.5) that says, "External clock mode 2 can be used with another trigger mode. For example, the ETR can be used as the external clock input, and a different input can be selected as trigger input (in trigger standard mode, trigger reset mode, or trigger gated mode)."
I would like to
- use TIM1_ETR as TIM1's clock (external clock mode 2)
- also use TIM1_ETR pin to reset/restart TIM5 (trigger reset mode)
- use TIM5 TRGO to reset TIM1 (trigger reset mode)
- pause or freeze TIM5 when it resets TIM1, until it is reset by TIM1_ETR
FWIW, my design constraints prevent me from simply polling the TIM1 counter in the main loop (there are plenty of examples for that), and I'd like more accuracy on when TIM1 is reset than what I can get from polling within a timer-driven ISR. Plus, I relish the challenge of learning the STM8S903 part and how its timers can be linked.
Is there anyone out there with experience on the STM8S903 that can confirm this configuration is possible and/or give hints on its implementation?