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Question asked by David Harrison on May 23, 2018
Latest reply on May 25, 2018 by avi_crak.videocrak

Hi, all. I am using a STM32F765VGT6 chip accessing a Macronix MX25L51245GZ2I 512Mbit (64MByte) NOR FLASH chip over the QUADSPI interface. I am using the HAL QUAD SPI driver. The AHB bus is running at 216MHz.

The problem I am seeing is very slow read access, even though I am using the QUAD SPI data transfer mode. I can't get above 1.8MBytes/second transfer speed, even when reading a block of 4096 Bytes. I am using Polled indirect read mode currently. The clock pre-scaler in the QSPI_HandleTypeDef data structure is set to 1 meaning a clock diver ratio of 2 and I do measure the QUAD SPI bus speed at about 100MHz using a logic analyzer. The data is being read correctly so the bus is actually working, just very slowly. With that high a clock speed, I should be getting a read data transfer rate of close to 50MBytes/second.


The odd thing is, that the measured data transfer rate stays at 1.8MBytes/second even when I increase the clock pre-scaler value, thus reducing the clock speed. It is not until I make the clock pre-scaler a ridiculously high value like 59, (divider ratio of 60) that the data transfer rate starts to fall below 1.8MBytes/second. So there is something else, other than the clock speed, that is limiting the data transfer rate and I can't figure out what that is.

Does anyone out there have any ideas of experience with this?