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STM32H7 SPI - trying to increase Master SS Idleness (MSSI) - affects only first transaction

Question asked by Yoav Biderman on May 24, 2018



I'm using the NUCLEO-H743ZI board with the STM32H743 MCU.

I'm using the HAL SPI1 module to transmit a buffer of 4 words (16 bits) and receive the corresponding 4 words into another buffer.

The component the MCU is communicating with (an A2D component), requires a certain delay between the active SS edge and the clock toggle beginning. Reading the reference manual, I noticed the MSSI parameter that's supposed to control this. When I set the parameter for 15 SPI clock cycles, it does create a delay, but only before the first word transaction and not the following 3 (image attached - SPI clock in yellow, SS in green).

Did anyone encounter this?