So, we are developing a camera-to-display interface STM32f769. Our EE has created an FPGA which is wired in to our STM32F7, giving us good VSYNC, HSYNC, DATA, and CLK pulses (verified by Salae). We have configured our DCMI peripheral (via the BSP functions BSP_CAMERA_Init, BSP_ContinuousStart, etc) to read in this data, configured our DMA2D peripheral to convert the incoming data from RGB565 to ARGB8888 , and then the output of the DMA2D is picked up by our DSI peripheral, which is driving our own little custom display.
Lots of links in this chain, but we were ecstatic to get it all working pretty quickly. Then we realized that when we increased the clock speed of the FPGA input to our DCMI from 20Khz to 30khz, we would hang after one frame. What was happening is that we would receive an IT_OVR interrupt ("indicates the overrun of data reception" -- not much info available) fro the DCMI peripheral, which causes the BSP functions to cancel the transfers.
Digging in to the BSP_CAMERA_Init function, it configures a DMA transfer. So really we have [external FPGA] -> DCMI->DMA-DMA2D->DSI->[external display]
So the first question is...
- Is it appropriate to use *both* DMA and DMA2D? Is this redundant? Should I instead configure DMA2D to be connected directly to the output of the DCMI? (i.e., should we be DCMI->DMA2D->DSI instead of DCMI->DMA->DMA2D->DSI?)
And the second question is
- What the heck is an overrun exactly, what causes the IT_OVR interrupt? What is being overrun? Is the DCMI receiving clock pulses too early? I feel like we are chasing a needle in a haystack without understanding exactly what this is, and it is *not* documented well.
Thanks very much for any insight!