Hello EE verse,
Can anyone explain the below implementation ?
I did see the reference to this function in the cortex_m4 generic reference manual but couldn't understand how the register is mapped.
Also no sure why in NVIC->ISER, IRQn (6 in my case) will be right shifted by 5? can you explain the logic?
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
if ((int32_t)(IRQn) >= 0)
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));