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AN4838 S field equivalent to non-cacheable

Question asked by greenwood.greg on May 17, 2018
Latest reply on May 18, 2018 by Khouloud G

In AN4838 it states on page 7/16:

The STM32F7 Series and
STM32H7 Series do not support hardware coherency. the S field is equivalent to non-cacheable memory.
Aside from the typo, I find this information to be confusing.  Does this mean that in F/H7 series devices that the S bit determines the cache behavior and is inter changeable with the C bit?  Or is it ignored?  Or is the S field and the S bit two different things?
Please clarify?

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