In AN4838 it states on page 7/16:
The STM32F7 Series and
STM32H7 Series do not support hardware coherency. the S field is equivalent to non-cacheable memory.
Aside from the typo, I find this information to be confusing. Does this mean that in F/H7 series devices that the S bit determines the cache behavior and is inter changeable with the C bit? Or is it ignored? Or is the S field and the S bit two different things?