It is about stm32f103 (RM0008). When the compare register becomes equal to the timer register,
output compare mode - if configured as set active, how to set inactive by the software?
Yes, if the software is fast enough not to miss the next edge, why not.
Or you could do it entirely in hardware, constructing a table of times, loaded into CCRx by DMA driven from that very same compare, using Toggle mode.
For example by changing its mode into Force Inactive. Or in timers which have this function, by an external signal on ETR (see TIMx_CCMRy.OCzCE).
Thanks. Actually my goal is to generate positive edges at dedicated time, let say 10 different slots in sequence...
Therefore the rising edge should be triggered by the hardware (timer) but the falling edge can be triggered by the software (because it ts not time-critical), when the next "time" has to be set in the CCR .
Is it correct to implement it in the following way:
- Output compare mode: as set active
- After the compare match (CCR==TIMx), change the output compare mode to Force Inactive, write new "time" to CCR and then set output compare mode back to set active?
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