I was looking at AN4661, pg 45 where the signal routing guidelines for SDMMC is given.
It has the below bullet points when it comes to skew
The skew being introduced into the clock system by unequal trace lengths and loads,
minimize the board skew, keep the trace lengths equal between the data and clock.
The maximum skew between data and clock should be below 250 ps @ 10mm
Now in an FR4 substrate, a general hand wavy calculations has 150ps for a 1inch (25.4mm) of mismatch between two lines. Going by this 250ps comes out to be 42mm of mismatch.
So I do not understand what "250ps @ 10mm " means? Can anyone explain?
Also is 250ps @ 10mm specification for high speed mode or default mode.
According to my understanding when SDIO operates at 50MHz, it called high speed mode and when running at 25MHz, its default mode. Correct me if I am wrong.
I have not been able to get the clock running at using STM32F765VI with an SD card. The clock divider bypass option seems disabled for SD card mode. Is it available only for eMMC mode?
With an SD card, am I limited to clock divider of 2. So it will always operate in default mode. Again, please correct me if I am wrong.
Last question: Is there any similar guideline for layout for the DCMI interface? In terms of max tolerated Skew (trace mismatch between clk and data lines)?