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DAP access to SRAM

Question asked by Ted Carter on May 8, 2018

Hi -


Is it possible for a debugger to directly r/w to embedded SRAM via one of the debug APs (access ports) on the stm32h7x3?  That is, I don't want to access SRAM via the M7 since the #cache might be enabled.  I'd like to inspect SRAM contents, not the cache. 


According to the TRM, AP0 is dedicated to the M7, so I assume SRAM access will be through the M7/cache.  AP1 (D3 AHB interconnect) looks right, but I did some experiments that suggesting that access is also through M7.   Could someone clarify?


Regards, Ted.