I use the STM32F030R8 as I2C slave with clock stretching. It is able to receive and send data based on interrupts. The transmission of the slave to the master works as long as the master and the slave know the same length of the data to be transmitted. I am currently looking for error handling if there is a misinterpretation, e.g. if slave and master expect different lengths during transmission from slave to master.
Therefore I have two cases.
l_m (data length that master expects to receive)
l_s (data length that is transferred from the slave)
1) l_m > l_s
2) l_m < l_s
Implementation of case 1) The bus hangs on a low SCL signal. This is because after the last byte transmitted by the slave, the master acknowledges it with an ACK instead of NACK and the slave thinks it must send more and because the clock streching is activated, the clock signal is forced to low and remains there.
Is there a way to handle this state on the slave side or even on the master side or do I have to reset the hardware?