I'm using an STM32F767 at 216 MHz with LL_FLASH_LATENCY_7. The IDE is Keil with IROM (Flash) at 0x8000000. STM documentation AN4667 says, "Flash memory is accessible by the CPU through ITCM starting from the address 0x00200000" and "Flash memory is accessible by the CPU through AXI starting from the address 0x08000000". Reviewing the Flash memory interface paths it's clear that the flash is accessed via AXI/AHB. The advice is "the instruction or/and data caches should be enabled in this configuration to get 0-wait-state-like access to the Flash".
I have added the line, "SCB_EnableICache();" to my SystemClock_Config function in file main.c.
Is that correct, sufficient and complete? I do not currently wish to cache data memory. I just want the same instruction fetch / execution performance increase I would have got from the ART accelerator in an STM32F4 for example.
I've searched the forum and STM documents and am now overwhelmed with information and seeking clarity.
thanks, John F.