is there a way to improve LSE drift on L4 Nucleo board? Or all I can do is to migrate to another crystal with higher precision?
Thanks, and regards
is there a way to improve LSE drift on L4 Nucleo board?
What drift? How do you know it's drifting?
RTC set by GPS, and after 24h time is wrong (a little bit). Better than LSI used before.
Little bits can be compensated by calibration.
Read the RTC smooth digital calibration chapter in RM.
I found the X-CUBE-RC-CALIB, but seems this is only for internal oscillators (LSI/HSI).
Found here a good thread.
Release Manual here. Section 38.3.12. Page 1230.
I'm not sure I can apply this method, since drift is higher than 448ppm.
Hi Gerardo Gallucci,
Please refer to AN2867: "Oscillator design guide for STM8AF/AL/S and STM32 microcontrollers".
if you are searching for minimum drift, you need to select Crystals with 12.5pF of CL they have teh best pullability factor versus the one of 6pF or 7pF that are more optimized for power consumption.( our nucleo board)
as well you need to adapt the right drive mode as our STM32L4 is able to have 4 drive modes from High to low depending on the usage : low drift or low power.
Also, CL1/CL2 capacitors should be trimmed at first design and PCB build to compensate the Cs ( stray capacitance) including the pads PC14/PC15 to reach the closest frequency of 32.768KHz , you can observe that at MCO level during this trimming and an universal counter.
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