On page 177 the definition of bits 4:0 and 12:8 of RCC_DCKCFGR appear to be incorrect.
Should these be PLLI2SDIVQ and PLLSAIDIVQ respectively?
Hello Bob Anderson ,
After check, there is a typo in the Bits 4:0 PLLI2SDIVRDIVR, it should be PLLI2SDIVR.
The RCC_DCKCFGR register, bits 12:8 are used for the divider from PLL and should be called PLLDIVR.
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