Using ADC1 and ADC2 in fast interleaved mode with dma transfering 32bit from ADC1.DR to memory in 32 bit device and mem mode (to handle both ADC1 and ADC2 data simultaneously as pr RM0008 and AN3116) delivers data that when plotted seems to be swapped. RM0008 sais the lower halfword will be ADC1 data and upper halfword will be ADC2 data. It also states ADC2 will start first and EOC interrupt will be generated by ADC1 which makes sence in that 2 samples are ten transfered every dma cycle in synch with ADC1.
Since the DMA can only increment memory and not decrement the data is thus listed like this when viewing the memory as array of 16 bit samples:
sample 2 (adc1 sample 1)
sample 1 (adc2 sample 1)
sample 4 (adc1 sample 2)
sample 3 (adc2 sample 2)
sample 6 (adc1 sample 3)
sample 5 (adc2 sample 3)
I tested by capturing a sinewave and it looks like sonic the hedgehog...
Swapping buffer with buffer, buffer with buffer and so on plots a nice wave.
I cannot find this in the errata as it does exactly as described. It is however not very useful...
Is there a workaround for this?
Am I triggering my ADC's wrong?
I am triggering the start of conversion in a odd way as I am using TIM1 slaved by TIM4 to generate a n-pulse train every 1ms and then using the end of the pulses as trigger for TIM3 which is just to collect the event and synchronize start of ADC since ADC1 cannot listen to TIM1_UPD which is generated when it reaches pulse count 0. (ADC can trigger regular channel conversion from T3_TRGO though, and using TIM3 I can have it trigger on TIM1_TRGO and deliver it's enable as T3_TRGO. I do not see how this can mess things up but you never know...