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DMA With TIM3

Question asked by sanjay kumawat on May 3, 2018
Latest reply on May 6, 2018 by waclawek.jan

waclawek.janNesrine MClive One

Hi all,

I have to generate a PWM signal of 15%,40KHz  with a short pulse in response with a input.

 

the task is, at initial the input state will be low. when input will become high then for 450us to 500us the output of should be high and then output switch to PWM signal of 15%,40Khz. and continue till input is high. As input becomes low the output should become low.

I have done it and it's running ok.

I have configure the input signal in interrupt mode for rising and falling edge both. and configured TIM3 Registers (PSC, ARR, CCR) for pwm 15%@ 40KHz.

The timer will continue run but I have put TIM3_CH1 at forced low mode at initial so output will low. when input will become high it will generate a interrupt and in ISR it will put TIM3_CH1 to Forced high mode  so output will high. and it will return from ISR to main function and will check for CC1IF bit state and count up to 20 (i.e. it will check for 20 pulses of 40Khz = 20*25us = 500 us). and when count will reach to >=20 it will put TIM3_CH1 to PWM Mode-1. and now pulses of 40KHz will start. and it works Ok. times of first pulse varies from 450us to 500 us but OK.

 

The input can be of UPTO 1200Hz freq.

My problem is that what I have done here is for 1 I/O set.

like this I have 5 I/O sets. each have to work like above. 4 Output  will share TIM3 (TIM3_CH1, TIM3_CH2....) and fifth channel will use different Timer.

I can do this same for these 5 I/O sets. but because of it check for CCxIF bit in main function in polling mode and count for 20 pulses to go. it creates problem in timing of first pulse if any interrupt comes. (it is ok from 450us to 500us but not out of it) .

Can DMA help here, can DMA perform this task that it checks 20 times of CCxIF bit and then generate a interrupt, actually I have never worked on DMA so don't know about it or any other suggestion.

 

You can find my code in attachment for 1 I/O set.

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