Is the code in HAL_PCDEx_SetTxFiFo() within stm32f7xx_hal_pcd_ex.c correct?
The datasheet says:
OTG device IN endpoint transmit FIFO size register
(OTG_DIEPTXFx) (x = 1..5[FS] /8[HS], where x is the
Bits 31:16 INEPTXFD: IN endpoint Tx FIFO depth
This value is in terms of 32-bit words.
Minimum value is 16
Bits 15:0 INEPTXSA: IN endpoint FIFOx transmit RAM start address
This field contains the memory start address for IN endpoint transmit FIFOx. The address
must be aligned with a 32-bit memory location.
However, HAL_PCDEx_SetTxFiFo isn't doing that (comments removed for brevity.)
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
uint8_t i = 0;
uint32_t Tx_Offset = 0;
Tx_Offset = hpcd->Instance->GRXFSIZ;
if(fifo == 0)
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
for (i = 0; i < (fifo - 1); i++)
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
i.e. the lower 16bits are addresses in bytes ; the upper 16bits are FIFO sizes in number of 32bit words.
There is no distinction in the HAL code between addresses which are in bytes and FIFO size which must be in 32bit words. The code ought to be multiplying by four for the Tx_Offset.
Tx_Offset = hpcd->Instance->GRXFSIZ << 2;
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 14);
I had been using Cube 1.9.0, but the same code is in 1.11.0.
If the code is correct, please educate me!