I am working with a system that can be expressed in such block diagram:
This setup works pretty well, but:
- Not on every instance of the device
- Sometimes it stops working, even though it was ok for couple days.
The reason for "not working" is that the I2C line become bricked somehow. In order to obtain that state, all I need to do is querry the slave on the other side of I2C buffer for presence. The osc views then look like this:
Note: The low level of SDA and SCL is not exatcly 0V, but around 0.7 V as described in P82B96 datasheet.
As you can see from the lower scope view, the slave ACK's (its address is 0x41) and releases the line (one can observe SDA line jump from 0V to 0.7V). The line should be pulled back to VCC but instead its held low, I believe by the master (STM32L4).
I am trying to understand this situation but I cannot figure this out. One things for sure- when the P82B96 I2C buffer is "shorted", the system works correctly. Using the buffer somehow interferes with masters I2C data parsing). The worst part is that this doesnt happen always, or starts to happen after a while.
I would appreciate all help in understanding this situation. Are there any cases in which master holds the data line low for some reason? Am I understanding this part correctly?