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Master clock generator in SAI1

Question asked by smalcom.alexandr on Apr 23, 2018
Latest reply on Apr 26, 2018 by smalcom.alexandr

Hello.

MCU: STM32L432KC. I'm trying to use SAI1 peripheral in master mode with master clock (MCLK) generation. I've found MCLK has drop pulses. You can see this at attached picture.
Clock configuration:
1. LSE with crystal 32768 Hz;
2. MSI with PLLMODE enabled;
3. RCC registers values:

CR = 0x0C0000BF
ICSCR = 0x106F008C
CFGR = 0x0
PLLCFGR = 0x00001071
PLLSAI1CFGR = 0xA8012B00
CCIPR = 0x0
CSR = 0x1C000600

Is i missed something?
Thanks.

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