I found an undocumented issue that's missing from RM0038 STM32L1 Rev 14. No note is made in AN4767 (though this doesn't pertain to L1, I take it to be general guidance for the family).
I'm using an STM32L151VE equipped with dual bank flash interfaces. Documentation is careful to say that processor stalls occur if writing to EEPROM in the same bank as instructions and recommends using the different banks to avoid this.
I've found this not to be true for unaligned EEPROM writes. Writing an EEPROM data word with 2-byte alignment in the second bank when executing instructions from the first bank stalls the processor.