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SPI Issues: NSS stays low, clk pol high toggling

Question asked by Steven Keeter on Apr 12, 2018
Latest reply on Apr 12, 2018 by Clive One

Using STM32F0 device and having some trouble with NSS hard output returning high after transaction, and also when using idle high clock polarity the preamble idle state is changing.  Sometimes it toggles high before start, other times it remains high until start.  I've seen comments about pull-up setting used on these pins and also seen comments on having to call De-Init after each spi transfer.  Seems the hardware should handle these???  When using NSS soft control the toggling of the clock polarity before spi transaction start seems problematic.