I have read a few short posts around this forum, that suggest disabling a timer in PWM/OC mode, will change the output pins to high impedance.
As background, I am trying to interface with a device that requires a PWM control pulse 500-2500us width as an input signal at 50-100Hz, The device replies with telemetry, on the same line, by creating a brief 1us wide pulse on the same line. The timing between the end of the control input pulse and the brief telem pulse determines the telem value (0.5ms equals zero and 5.5ms is fullscale). There is a cycle of 11 telem values. The cycle start is marked, by the device not sending a telem pulse, followed by 11 replies.
Device interface spec, includes that i must yield the line (high impedance) after generating the control pulse and use a 2k pullup on my end for my 3.3V logic.
I would like to send the control input pulse using a ONESHOT mode timer that is triggered based on another timer that is not relevant to this discussion.
If i disable the ONESHOT timer at the end of its pulse (end of pulse callback), will its output go high impedance? I have a scheme, based on another input capture timer to measure the telem value timing and on its input capture callback, can i simply re-enable the ONESHOT timer and have it ready for the next trigger event?
I am looking for confirmation from somebody who has done something similar or can confirm that temporarily disabling a timer changes it output to high impedance and simple re enable will reverse that and timer will function on next event.
If disabling the timer, does not set out to High impedance, i am open to suggestions. Obviously, i can add external components, tristate buffer/driver, but i am looking for soft solution before adding hardware.