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Update Interrupts & Race Conditions

Question asked by Dennis Ai on Mar 30, 2018
Latest reply on Mar 30, 2018 by dhenry



I am using a STM32F767Z MCU at the moment, and wanted to understand better understand how update interrupts work.  Specifically:


  • I have configured TIM1 to create an update interrupt when the counter overflows (upcounting mode).  TIM1 is set to Master Mode, and TRGO is set to the update event.
  • TIM2 is set to Slave Mode - Combined Reset Trigger Mode, and has one PWM output on Channel 1.  I set TIM2_CCR1 to determine the duty cycle.
  • In my update interrupt, I would like to update the value of TIM2_CCR1 to modify the duty cycle of PWM Channel 1 on TIM2.


I have a few questions regarding this configuration.


  1. If I do not set the preload bit for TIM2 PWM Channel 1, and TIM2_CCR1 is already set to some small value (e.g. a value corresponding to 1 microsecond), is it possible that my update interrupt will fail to modify TIM2_CCR1 before the counter reaches the existing value in TIM2_CCR1?
  2. If I set the preload bit for TIM2 PWM Channel 1, then which happens first?  The modification of the TIM2_CCR1 preload register with the update interrupt, or the loading of the preload register into the shadow register due to the Reset Mode that TIM2 is configured to?


In other words, what type of overhead is associated with update interrupts, is it predictable, and can it cause a race condition in the scenario above?