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SPIRIT1 interrupt status register bits

Question asked by Gergo Santha on Mar 28, 2018



My SPIRIT1 code is not working properly and I found confusing the description of the INTERRUPT_MASK and INTERRUPT_STATUS registers in the SPIRIT1 datasheet (rev 10, Oct 2016). In the registers description both MASK[3:0] and STATUS[3:0] registers refer to Table 36. For me that means setting bit 6 in MASK[0] register is flagged in bit 6 of STATUS[0] register.


However, in the Spirit1 library provided by ST, in the SPIRIT_Regs.h file, the relation is reversed, MASK[0] is reflected in STATUS[3].  Which one is true?


I also have a strange problem, when reading the 4 IRQ_STATUS register content. I initially thought that if I set a bit in MASK (and the others are all zeroes) then in the STATUS register only that bit will flag if the event occurs. However when I read the STATUS registers I get other bits set indicating that other events are also occured. Is that a normal behaviour?


Thank you!