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STM32 CAN bus "bit dominant error" meaning

Question asked by sdt99 on Mar 23, 2018
Latest reply on Mar 24, 2018 by Clive One

I understand a high speed CAN bus bit error means that while I am transmitting a bit outside of the arbitration period I sense the opposite bit on the bus.   However STM gives two bit errors: "bit dominant error" and "bit recessive error", and I'm not sure what they each mean:

 

Does "bit dominant error" mean "While I was transmitting a dominant bit the bus was sensed as recessive"   or does it mean "While I was transmitting a recessive bit the bus was sensed as dominant" ?

 

Thanks

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