I'm using SPL libs for stm32F103RB in a nucleo board. I was creating a first ADC level driver and testing.
After configuring individual, regular and scan mode adc group channels, so dma with the correct values the conversions seem to be working. I have adc1 channels, from channel 9 to channel 15, so I used:
ADC_RegularChannelConfig(ADC1, ADC_Channel_9, 1, ADC_SampleTime_55Cycles5);
...(ADC1, ... , ++, ADC_SampleTime_55Cycles5);
ADC_RegularChannelConfig(ADC1, ADC_Channel_15, 7, ADC_SampleTime_55Cycles5);
So DMA is configured as:
#define ADC1_DR_ADDR ((uint32_t)0x4001244C)
DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address;
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)regularConvData_Tab;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStructure.DMA_BufferSize = 7;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
The fact is that when I read regularConvData_Tab, debugging, after varying voltage values at input channels I can see how the converions are done propperly.
But there happens anotherthing weird:
Now, I was varying the voltage value input pins, one by one. And I could observe that channel_12 end conversion value has been transfered and saved at first memory address, channel_13 at second, 14 at next, 15 at fourth, 9 channel at 5th, 10 at sixth and 11 at the last. I observed it looking into regularConvData_Tab[index] array.
It seems to be starting dma transfer at channel_12 end conversion, instead by channel_9, which it was programmed to be the rank = number 1 at the sequence of conversion.
order in channel conversion seq index channel content order in regularConvData_Tab[index]
chn 9 0 chn 12
chn 10 1 chn 13
chn 11 2 chn 14
chn 12 3 chn 15
chn 13 4 chn 9
chn 14 5 chn 10
chn 15 6 chn 11
Has any body explanation for this behaviour?
I have deeply read adc and dma chapters in datasheet, but I only see that dma and adc seems to be correctly configurated and I don't understand this type of transfer offset.
How can be chn 9 ending conversion and transfering to dma after chn 12 or chn 15 doing it, in example?