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stm32Fxxx ICT using JTAG

Question asked by boyd.richard on Mar 15, 2018
Latest reply on Mar 15, 2018 by Andrew Neil

To begin, this is a board TEST question rather than a design question: Has anyone successfully generated digital In-Circuit Test vectors for the STM32F4xx families using the Keysight 3070 or Teradyne scan tools? I successfully modeled the part describing the cortex and Jtag cores in a part description library - this way both core's instruction registers are accounted for etc, however it didnt' work in practice.  Bottom line, i just get NOTHING out of TDO during test. I can successfully program the parts all day with the st-link v2 pod, so i know signal and device integrity is good. but board test is another matter.  This makes me wonder if there are unpublished compliance pins besides nrst.   So question to the forums - anyone out there doing board test? if so any boundary scan successes to report? i have had sucess with the STM32F103RB, but the 407 i'm getting nowhere.  thoughts?

 

regards

RB

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