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Sensible Configuration for Timer Triggered Continuous STM32F4 ADC Sampling

Question asked by Seng Tak Goh on Mar 15, 2018
Latest reply on Mar 15, 2018 by Seng Tak Goh

Hi all,

 

I am about the configure the timer frequency which will trigger ADC to continuously scan and convert 5 channels. The callback will be from DMA.

 

The MCU I am using is STM32F407. System core clock is 168 Mhz. Fpclk1 = 42MHz, Fpclk2 = 84MHz...

 

A question came up when setting the ADC clock prescaler, and the overall configuration between the timer frequency and ADC settings. What would be the max or logical value?

 

 

My idea is as follow, please help to comment or correct me if I am wrong, without considering the external impedance.

 

I wanted to trigger the ADC every 84 kHz from a selected timer.

There are 5 channels to scan and convert in a row, 12 bit resolution and 15 sampling cycles for each channel.

 

Understanding from datasheet that typical fadc is 30 MHz, so does this mean that a sensible set of configuration would be limited by the following parameters:

  1. Fadc prescaler should be >=4 ?
  2. Timer frequency should be <= ( Fadc / ( channel_cnt * ( sample_cycle + conversion_cycle  )  )?

 

Thank you.

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