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Jitter less than 20ns with STM32L476

Question asked by bardeau tracy on Mar 8, 2018
Latest reply on Mar 10, 2018 by T J

Hi,

I've a problem with the jitter of my program on STM32L476.

First of all, I'm introduced you my project.

A signal TLL with a frequency of 1KHz to 50 KHz must be multiplied by a sinusoide or square analogique signal (10Hz to 1KHz) like a AM modulation. Then with the DAC of STM32 a results could be send in analogique format.

 

at the beginning I'm use a DMA for the ADC/DAC and a callback function trig by timer 6 (sampling Time 100 Khz).

In a call back function I'm get the state of the TTL and multiplied by the results of ADC (result *1 if the TTL state was SET or result *-1 if the results state is RESET), then I get the result in the DAC.

 

When I look the result with an osciloscope I see a 8 µs jitter and the frequency results is so bad especially near 50 Khz. period for 50Khz is 20 µs so sometime I see 35 KHz and sometime 80 KHz.

 

So I have modified my code like that. I made a new extern interuption on signal TTL and change the state of a variable 1 then -1. I use freeRTOS and give the high priority to the EXTI interupt. In a callback TIMER 6 i use the result of the ADC multiplied by the variable 1 or -1.

 

When I look the result with an osciloscope I see a 100ns jitter for the EXTI interrupt and always 8 µs jitter for the final results.

 So my question is what is the minimal jitter I could have for my project?

I don't know really freeRTOS and i do'nt understand why i can't get a prioity value less than 5. This is a probem because i want the maximum priority to the EXTI interrupts to reduced the jitter.

 

Can I do like that:

only one interruption EXTI on signal TTL (between 1 to 50 Khz).

in the function of EXTI :

I manually start the DAC with the value of ADC( The first conversation could be wrong but it doesn't matter)

Then I manually START ADC (one sample)

I change the state of a variable example stateTTL = StateTTL * -1 to change 1 in -1 or -1 in 1.

I multiplied the value of ADC by stateTTL.

 

I think when I do like that I have the jitter of only the EXTI interrupts + the DAC jitter isn't it?

I want a precison of 50 Hz at 50KHz so I must have a global jitter less than 20ns. It is Possible?

Thank you for your answear.

 

here i attached a schema

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