Hello friends,How is possible Can Master and Slave protocol in STM32CubeMX?is it corresponding situation?
No, there are no masters or slave in CAN, only priorized addresses/IDs.
I believe that you are refering to naming of CAN interfaces in STM32CubeMX. This is correct that you can see there that some of CAN interfaces are marked as master and some are marked as slaves. This naming is misleading, becasue principle of CAN is not master-slave architecture, but multi-master architecture. And so it is for all CAN interfaces in STM32 MCUs. This master-slave naming in STM32CubeMX refers to relationship between CAN modules in STM32. If there is more than one CAN in MCU, then always one acts as a master and rest of them act as slaves. This should be understood in this way: CAN peripherals in single STM32 MCU share some of common resources: some RAM memory and CAN filtering. CAN master is in charge of these resources. CAN slaves are full featured CAN peripherals, but in order to configure filtering for them you need at least to enable clock for CAN master.
I also looked the reference manual ,now as much as I understand no problem to use master to master CAN between any devices.
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