I am getting some results that I do not entirely understand using this accelerometer. Bypass mode works fine, I can see the gforce data and see it change as expected. I am now working with FIFO mode, but I am having some issues. After I do all the register configuration writes, I then wait for the ZYXDA bit to assert before I make a read from the FIFO. If I just put this in a loop, then I read the same value over and over.
1)wait for ZYXDA
2)read OUT registers
3) goto 1)
If I actually wait for ZYXDA to assert, and then perform TWO reads, then the data changes. (When I say a read, I mean reading 6 bytes, each H and L byte for each axis. I do this in a burst and it is working since the bypass mode is working). If I understand it correctly, there is a 32 level FIFO for each channel. And that when you read the OUT_X_L, OUT_Y_L, etc. registers, it will give you the value of the contents of the FIFO pointer and increment. Is this correct? I have lots of debug code in now, and am seeing stuff I do not understand. For example, once I detect ZYXDA is high, I then grab the contents of STATUS_REG and FIFO_SRC_REG. Right before I read for the first time, the STATUS REG reads 0xFF and the FIFO SRC REG reads 0x20. So it is saying there is data ready, that there is an overrun, and that the fifo is empty. This does not make sense if there is data ready, shouldn't the FIFO count be at least 0x01? The second time it sees ZYXDA asserted, then the registers look better: STATUS REG is 0x0F and FIFO SRC REG is 0x8E for example. If I then keep doing single reads I can see the FIFO count decrease as I make each read and increase if I let it fill up. If the FIFO becomes full, then I can read the contents out one by one and it looks like their hardware does not update the FIFO. I can see the fifo count countdown, but if I wait a bit of time for the FIFO to fill back up and count increase, the FIFO count does not change. I then read the rest of the bytes out of the FIFO until it is empty. I assume the FIFO is in bypass mode and I need to write the FIFO CTRL REG again to put it back in FIFO mode. So my question is why it takes TWO FIFO reads at the beginning to get it going?
Below is my init code. I guess I could just read the FIFO twice to start out, but I would like to understand the functionality.
writeRegister8(ACC_FIFO_CTRL_REG,0x0); //Bypass mode to reset
writeRegister8(ACC_CTRL_REG1,0x1F); //Enable XYZ Axis, enable LP mode,1Hz
writeRegister8(ACC_CTRL_REG3,0x40); //Enable IA1 pin interrupt
writeRegister8(ACC_INT1_CFG,0x6A); //Enable Int1 for any axis change, above threshold
//writeRegister8(ACC_CTRL_REG5,0x04); //4D enable
writeRegister8(ACC_FIFO_CTRL_REG,0x40); //FIFO mode
writeRegister8(ACC_CTRL_REG5,0x44); //Enable FIFO