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STM32 SDADC phase delay ?

Question asked by schweizer.roger on Feb 28, 2018
Latest reply on Mar 1, 2018 by schweizer.roger
Hello everybody
Does anyone have experience with the SDADC of the STM32F373?

I have the following question:

Theoretically, my phase delay would have to be at a
Sampling frequency of 50kHz and output to the 12bit DAC be as follows:

My input circuit OPAmp with filter 2700Ohm 330pF = ca.1us
SDADC input (impedance 120kOhm 0.7pF) delay = ca.T = 120kOhm * 0.7pF = 0.08us
SDADC conversion time = 1 / fs = 1 / 50kHz = 20us
DAC (with buffer) tSettling = 4us
Reconstruction filter RC = 680Ohm 10nF = delay = 680Ohm x 10nF = ca.7us
My C-code measured = 5us
1us +
0.08us +
20us +
4us +
5 us +
7us =

But I measure with Oscilloscope 55us!
I reach the required bandwidth of 10kHz. On the KO I see too
the 5 steps at 10kHz (50kHz sampling rate). That proves that I have correctly configured the SDADC. I just can not get the theoretical phase time.

Can someone tell me where this difference comes from?