AnsweredAssumed Answered

PLL won't lock, HW vs FW

Question asked by Ryan Cope on Feb 24, 2018
Latest reply on Mar 6, 2018 by Ryan Cope

Hello,

 

I've been working with the ST25RU3993  on a user board design and have not yet been successful in getting the PLL to lock.  

 

I've tried to set the VCO range both manually and with the auto command.  I've tried a variety of combinations of carrier frequency/base frequency/reference frequency settings.  

 

In trying to troubleshoot the problem I've noticed that I only get a voltage waveform on VDD_B with the default PLL settings and a reference frequency of 100kHz.  Attempts to calculate the N divider and change the settings in registers 17, 18, 19 result in reading of zero on VDD_B.  In all testing so far I have only seen a few millivolts on VDD_A, however I understand that could be just because the PLL has not locked yet.  Can anyone tell me what I should expect to see on VDD_B as I seek the correct N divider and a locked PLL?  Is it even reasonable to assume I can infer anything about the PLL based on the waveform seen on VDD_B?

 

As far as hardware goes SPI and IRQ communication is ok and no clock issues.  My one concern is the external loop filter.  I'm using default settings for the internal filter and external values of 15kohms, 3.9nF, and 150pF per the Radon board documentation.  The external filter is about 3/4 inch from the IC reader so placement is not ideal.  Could placement of the filter on the board impact it's function to the point that it's values would be drastically different than an eval board?  Could poor placement of the filter ruin any chances of getting the PLL to lock at all?

 

Thanks,

 

Ryan

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