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Timer 2,3 Offset

Question asked by roofie01 on Feb 20, 2018
Latest reply on Feb 25, 2018 by roofie01

Here's my code to initialize timers 2 and 3. Keep in mind that right now, this code executes with no problem and there is a 100Hz output on PA5 (TIM2) and PA6 (TIM3)

My objective is to offset TIM3 by 180 degrees from TIM2. I am able to do this in SPL, but have had no success with LL after trying different things, including direct register writes to TIM2 and TIM3. The interrupt handlers are functioning OK for both timers.

 

What do I need to do to the code below to achieve this?

 

 

__STATIC_INLINE void  Configure_TIMPWMOutput(void)
{
  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
 
  /* GPIO TIM2_CH1 configuration */
  LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_5, LL_GPIO_MODE_ALTERNATE);
  LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_5, LL_GPIO_PULL_DOWN);
  LL_GPIO_SetPinSpeed(GPIOA, LL_GPIO_PIN_5, LL_GPIO_SPEED_FREQ_HIGH);
  LL_GPIO_SetAFPin_0_7(GPIOA, LL_GPIO_PIN_5, LL_GPIO_AF_1);
 
  /* GPIO TIM3_CH1 configuration */
  LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_6, LL_GPIO_MODE_ALTERNATE);
  LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_6, LL_GPIO_PULL_DOWN);
  LL_GPIO_SetPinSpeed(GPIOA, LL_GPIO_PIN_6, LL_GPIO_SPEED_FREQ_HIGH);
  LL_GPIO_SetAFPin_0_7(GPIOA, LL_GPIO_PIN_6, LL_GPIO_AF_2);  
 
  /***********************************************/
  /* Configure NVIC for TIM2 interrupt */
  /***********************************************/
  NVIC_SetPriority(TIM2_IRQn, 0);
  NVIC_SetPriority(TIM3_IRQn, 0);
    
  /******************************/
  /* Peripheral clocks enabling */
  /******************************/
  /* Enable timer 2 peripheral clock */
  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
  /* Enable timer 3 peripheral clock */  
  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3);   
 
  /***************************/
  /* Time base configuration */
  /***************************/
  /* Set the pre-scaler value to have TIM2 counter clock equal to 10 kHz */
  LL_TIM_SetPrescaler(TIM2, __LL_TIM_CALC_PSC(SystemCoreClock, 10000));
  LL_TIM_SetPrescaler(TIM3, __LL_TIM_CALC_PSC(SystemCoreClock, 10000));  
 
  /* Enable TIM2_ARR and TIM3_ARR register preload. */
  LL_TIM_EnableARRPreload(TIM2);
  LL_TIM_EnableARRPreload(TIM3);  
    
  /* Set the auto-reload value to have a counter frequency of 100 Hz */
  LL_TIM_SetAutoReload(TIM2, __LL_TIM_CALC_ARR(SystemCoreClock, LL_TIM_GetPrescaler(TIM2), 100));
  LL_TIM_SetAutoReload(TIM3, __LL_TIM_CALC_ARR(SystemCoreClock, LL_TIM_GetPrescaler(TIM3), 100));  
 
  /*********************************/
  /* Output waveform configuration */
  /*********************************/
  /* Set output mode */
  LL_TIM_OC_SetMode(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_OCMODE_PWM1);
  LL_TIM_OC_SetMode(TIM3, LL_TIM_CHANNEL_CH1, LL_TIM_OCMODE_PWM1);  
 
  /* Set output channel polarity */
  LL_TIM_OC_SetPolarity(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_OCPOLARITY_HIGH);
 
  /* Set compare value to half of the counter period (50% duty cycle ) */
  LL_TIM_OC_SetCompareCH1(TIM2, (LL_TIM_GetAutoReload(TIM2) / 2));
  LL_TIM_OC_SetCompareCH1(TIM3, (LL_TIM_GetAutoReload(TIM3) / 2));  
 
  /* Enable TIM2_CCR1 register preload.   */
  LL_TIM_OC_EnablePreload(TIM2, LL_TIM_CHANNEL_CH1);
  LL_TIM_OC_EnablePreload(TIM3, LL_TIM_CHANNEL_CH1);  
 
  /**************************/
  /* TIM2 and TIM3 interrupts set-up */
  /**************************/
  /* Enable the capture/compare interrupt for TIM2, TIM3 channel 1*/
  LL_TIM_EnableIT_CC1(TIM2);
  LL_TIM_EnableIT_CC1(TIM3);    
 
  /**********************************/
  /* Start output signal generation */
  /**********************************/
  /* Enable TIM2, TIM3 output channel 1 */
  LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH1);
  LL_TIM_CC_EnableChannel(TIM3, LL_TIM_CHANNEL_CH1);  
 
  /* Enable counters */
  LL_TIM_EnableCounter(TIM2);
  LL_TIM_EnableCounter(TIM3);    
 
  /***********************************************/
  /* Enable TIM2 and TIM3 INT Handlers */
  /***********************************************/
  NVIC_EnableIRQ(TIM2_IRQn);
  NVIC_EnableIRQ(TIM3_IRQn);
 
  /* Force update generation */
  LL_TIM_GenerateEvent_UPDATE(TIM2);
  LL_TIM_GenerateEvent_UPDATE(TIM3);  
}

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