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Understanding FMC/SDRAM Clock Timings

Question asked by Terence D on Feb 18, 2018
Latest reply on Feb 20, 2018 by Terence D

Hi, I've been dissecting the FMC_SDRAM example that comes with the STM32CubeF4 package.  I'm using the STM32F429 Discovery board.  The SDRAM chip it has on it is an ISSI IS42S16400J-7TL.

 

One thing I don't understand are some of the comments in the main.c file of the FMC_SDRAM example with respect to timing configurations.  The code sets up the AHB to run at 180 MHz, but a comment in the code says:

 

/* Timing configuration for 90 MHz of SDRAM clock frequency (180MHz/2) */

 

I don't understand why they're saying the configuration is for 90 MHz when the clock is configured to 180 MHz. 

 

Additionally, when configuring the SDRAM timings, it will make comments like in the following code:

 

/* TXSR: min=70ns (6x11.90ns) */

SDRAM_Timing.ExitSelfRefreshDelay = 7;  // 7 clock cycles

 

I have the ISSI IS42S16400J datasheet and understand the "Exit Self-Refresh to Active Time" is 70 ns.  However, I don't understand what is meant by the "6 x 11.90ns" comment and how they come up with 7 clock cycles as the setting.

 

At 180 MHz, I would expect a single clock cycle to be 5.55 ns (i.e. 1 second divided by 180,000,000) and therefore the SDRAM_Timing.ExitSelfRefreshDelay to get set to 13 clock cycles.

 

Can someone please tell me what I'm misunderstanding here?  Thank you.

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