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CAN Filter passes more messages as defined

Question asked by LookUpTable on Feb 17, 2018
Latest reply on Feb 19, 2018 by Ben K

I have a problem with STM32F042 CAN Filter mechanism. Basically the CAN is working. I can send and receive messages. But my filter are passing more messages to the FIFO as defined. This is leading to an overrun.Proved by the status bits. I carefully read the register in the reference manual and can not find what I am doing wrong. Here is my code

 

void initCAN(void){
     RCC->APB1ENR|=RCC_APB1ENR_CANEN;                                     // enable CAN clk
     CAN->MCR |= CAN_MCR_INRQ;                                       // Enter CAN init mode to write the configuration
     while ((CAN->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {        // Wait the init mode entering
          /* add time out here for a robust application */
     }
    CAN->MCR &=~ CAN_MCR_SLEEP;                                     // Exit sleep mode
     CAN->BTR &= ~CAN_BTR_TS1_0;                                    // reset Bit0 and Bit1
     CAN->BTR &= ~CAN_BTR_TS1_1;
     CAN->BTR &= ~CAN_BTR_TS2_1;                                     // reset Bit 1 in TS2
     CAN->BTR |=  0x1 << 20 | 0x4 << 16 | 0x02F << 0;       // set timing to 125kb/s@75%: BS1 = 5, BS2 = 2, prescaler = 48                
     CAN->MCR &=~ CAN_MCR_INRQ;                           // Leave init mode
     while ((CAN->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)    // Wait the init mode leaving
     {
          /* add time out here for a robust application */
     }

     CAN->FMR |= CAN_FMR_FINIT;                                             // enter Filter init mode
    CAN->FA1R &= ~(uint32_t)(CAN_FA1R_FACT0|CAN_FA1R_FACT1);      // deactivate filter 0 and 1
     CAN->FS1R|=CAN_FS1R_FSC0;                                               // Teo single 32 bit register on filterbank 0
     CAN->sFilterRegister[0].FR1 = (uint32_t)(13)<<21 ;                // only IDs with stdID 13 should pass
     CAN->sFilterRegister[0].FR2 = (uint32_t)(14)<<21;               // only IDs with stdID 14 should pass
     CAN->FM1R |= CAN_FM1R_FBM0;                                         // Filterbank 0 in ID List mode
     CAN->FFA1R|=0x03;                                                       // route Filteroutput 0 and 1 to FIFO 1
     CAN->FA1R |= CAN_FA1R_FACT0|CAN_FA1R_FACT1;                     // activate Filter 0 and 1
     CAN->FMR &=~ CAN_FMR_FINIT;                                         // leave filterinit mode
}

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