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Flushing fifo and transmitting remaining DMA data(Quick question)

Question asked by piet t on Feb 17, 2018

Hey everyone,

 

I have a circular double buffer DMA  set up, the data coming into the buffer can stop at any time, I also have a fifo setup.

 

Once the data stops I have a callback that's called, I just want to make sure about how I'm clearing the fifo and data.

 

 

From the reference manual, to flush the FIFO I need to reset the enable bit.

 

So basically disable the DMA stream and then re-enable it and the fifo will flush the data to the destination?

 

From this I can also tell that if its less than the threshold, single transactions will take place till all new data is out.

 

After this I can find the buffer that's being used by looking at the  DMA_SxCR regiser, bit 19 and the amount of data that's been read in by looking at the DMA_SxNDTR register(Taking the buffer value and subtracting this value)

 

Thanks in advance for any clarification and help.

 

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