We are using a STM32F071V8 MCU in our project. I am polling the ADC to read the data and have followed the following procedure to initialize the ADC:
1. enable clock to respective GPIOs
2. Initialize GPIO pins as Analog Inputs
3. Turn on HSI14MHZ clock
4. enable clock going to ADC
5. reset ADC
6. begin ADC calibration
7. wait for calibration to finish
8. enable the ADC
9. enable the VBAT divider and temperature sensor
10. Configure the sampling time
11. Configure ADC_CFGR1 register for settings - 12 bit resolution; Analog WDT disabled; Sinlge conversion mode
12. Configure ADC_CFGR2 register for settings - ADCCLK (Asynchronous clock mode)
13. wait for ADC to finish starting up
I was trying to determine the value of VDDA by using the formula below:
VDDA = 3.3 V x VREFINT_CAL / VREFINT_DATA
The VREFINT_CAL value read is 1519. Upon reading the ADC_DR register after calibration I found the calibration factor to be 0x42.
When I poll for the data on the ADC_IN17 channel it varies drastically with respect to the sampling time.
Please find the results below:
SMP[2:0] = 000: 1.5 ADC clock cycles ; ADC counts = 1891; VDDA = 2.26V
001: 7.5 ADC clock cycles ; ADC counts = 1657; VDDA = 3.06V
010: 13.5 ADC clock cycles;ADC counts = 1383; VDDA = 3.6V (Worse!)
011: 28.5 ADC clock cycles;ADC counts = 1510; VDDA = 3.319V
Remains almost same for higher sampling time.
Could you please help me draw an inference here?
Thanks in advance.