I have generated project from STM32CubeMX, FreeRTOS and Ethernet. I have working Ethernet with websockets, SDIO SD card and SPI1.
On SPI1 bus I use optocouplers for galvanic isolation and I need to use the slowest SPI1 clock (so I get nice digitale edges on the optocouplers) but the fastest CPU speed (to handle many things). So HCLK is 168 MHz and by /16 divider on APB2 and 256 divider in SPI peripheral I can get the desired maximal frequency 41 kHz, but the ethernet stops functioning. In UART console I see transmitting DHCP requests in a loop every 4 / 8/ 16 seconds..
When I use APB2 divider /2 /4 /8 it works ok and I get interrupts from ETH, but the /16 divider breaks the ethernet.
When I use APB2 /16 divider, the I no longer see the transmitting packets with a scope on TXD0/1 or RMII, on RXD0/1 I see some incoming network traffic. The code also don't jump to the ETH IRQ handler (probably because no DHCP request is sent)
Systick which is calling osSystickHandler works ok
TIM14 IRQ which is on APB1 is calling HAL_IncTick is ok.
MDIO/MDC communication with PHY is ok and I see the end of autonegotiation with a scope on the wires.
I've attached the picture with clock tree and scope traces for /8 where you can see RMII_TX communication and with /16 divider where the TX_EN pulse is suspiciously shorter and without any TX data.
Dividing APB1 bus by /16 is ok, so If I don't find solution the I could try to use SPI2 which is on APB1 which is fine if I enable /16 divider. But if anyone has another idea of workaround, that would be nice.
I need to use optocouplers for low price, I know about iCouplers and other capacitative and inductive galvanic isolators but it is not possible to use them because of the price and also because I use just 12 V rail/logic on the output side. Also I would be ok with 5kHz SPI clock, but aparently the F4 has all the peripherals clock derived form HCLK.
Thank you for any tips/ideas.