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DTCM and SRAM parallel access

Question asked by piet t on Feb 8, 2018
Latest reply on Feb 10, 2018 by piet t

Hey everyone,

 

I'm using a STM32f722ZE.

 

I wanted to know if I allocate two 32KB buffers. One being in SRAM1 and the other in DTCM, With a double buffer DMA2, can the CPU and DMA run in parallel? To my understanding they can. So as soon as the buffer is filled in SRAM2, the DMA will shift to fill the buffer in DTCM and the CPU can process the data in SRAM2. Then the can sort of do this handshake while avoiding collisions on the bus.

 

STM32F722ZE bus matrix

 

Same thing with AHB1 and AHB2, the DMA2 can access AHB1, while the CPU accesses AHB2, all in parallel?

 

This is my understanding of the busmatrix. The collisions in requests only occur when the same space in the bus is accessed, i.e. Both targeting AHB1 .

 

Thanks in advance for any clarification

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