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Occasional runt I2C 9th clock edge.

Question asked by Peter Morrow on Feb 7, 2018
Latest reply on Feb 8, 2018 by Peter Morrow



We are running a system with a single F7 I2C master and a number of F0 based I2C slaves (currently 4 slaves), each slave is connected to the master via ~0.3m cables.  We are using 10-bit addressing.


We are seeing a very intermittent issue where the the 9th clock edge does not rise very high (0.7v), all previous clocks are OK.  It seems that this then confuses the slaves I2C statemachine and SDA stays low.  Please see the attached logic shot.


Is this a known issue?  We are seriously scratching our heads here as this has been troubling us for a number of weeks now.