According to the datasheet, the GPIO ports circuit diagram looks like this in STM323L4x2:
From this diagram I understand that at powerdown (VCC = VSS = 0 V) the I/O pin state is high impedance. But is that 100% correct? I want to make sure before I make a design move that would save me some components. But for this I need to know either there are no internal pull-downs on a pin when the MCU is powered down.
I would appreciate all help.