Again, a question/request to ST:
PLL output dividers' desctiptions contain this warning:
These bits should be written only if PLL is disabled.
Is there any deeper underlying reason for this, or is this only to prevent transient functional irregularities in attached peripherals due to gliches on clock (i.e pulses shorter than any of the old and new halfperiod) during the switching?
In other words, if there's no active peripheral attached to given clock, may it be safe to switch it on the fly? Or will that result in the PLL/whole chip grinding to halt and catch fire?
The particular reason why I'm asking is, that in STM32F446, if SPDIF-Rx is clocked from PLL_R, after detecting the incoming SPDIF stream's speed (at maximum required clock), if the incoming stream is slow, the clock could be throttled back to reduce consumption and EMI. SPDIF-Rx itself does not have a clock divider; and it does not need to be active at the moment of speed switching, but PLL itself can't be switched off if used also as a primary clock source to the rest of the chip.
But there may be other scenarios where relaxing the above requirement to "don't change these bits while there's an active peripheral connected to this output" may be beneficial, so if there's no particular reason to be strict, please consider this change.
And please comment.