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CubeMX 4.23.0 bug STM32H743

Question asked by Joerg Wagner on Jan 7, 2018

When your application uses SRAM3 (0x30040000) in D2 domain,

it's a must to enable the clock for the domain. I cannot find an option in CubeMX

and CubeMX does not generate the important code line.

SRAM3 is used for Ethernet for example.

 

The modified SystemClock_Config() function must be like this:

 

/** System Clock Configuration
*/
void SystemClock_Config(void)
{
      RCC_ClkInitTypeDef RCC_ClkInitStruct;
      RCC_OscInitTypeDef RCC_OscInitStruct;
      HAL_StatusTypeDef ret = HAL_OK;

 

      /*!< Supply configuration update enable */
      MODIFY_REG(PWR->CR3, PWR_CR3_SCUEN, 0);

 

      /* The voltage scaling allows optimizing the power consumption when the device is
         clocked below the maximum system frequency, to update the voltage scaling value
         regarding system frequency refer to product datasheet.  */
      __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);

 

      while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {}

 

      /* Enable D2 domain SRAM3 Clock (0x30040000 AXI)*/
      __HAL_RCC_D2SRAM3_CLK_ENABLE();

 

      /* Enable HSE Oscillator and activate PLL with HSE as source */

...

 

Comparing HAL examples and CubeMX code (both 400MHz), there are another differences:

 

HAL:

 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);

CubeMX:

 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);

 

HAL:

       RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;

CubeMX:

       RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;

 

In my opinion it should be:

RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1;

 

PLLM1 = 4 (labelled as DIVM1 on page 295 in RM0433 ), PLLM1 is set to 4 in some HAL examples and CubeMX code.

HSE=8 MHz / DIVM1 = 2 MHz

 

RM0433 page 354:

 

Bits 3:2 PLL1RGE[1:0]: PLL1 input frequency range
Set and reset by software to select the proper reference frequency range used for PLL1.
This bit must be written before enabling the PLL1.
00: The PLL1 input (ref1_ck) clock range frequency is between 1 and 2 MHz (default after reset)
01: The PLL1 input (ref1_ck) clock range frequency is between 2 and 4 MHz
10: The PLL1 input (ref1_ck) clock range frequency is between 4 and 8 MHz
11: The PLL1 input (ref1_ck) clock range frequency is between 8 and 16 MHz

 

- Joerg -

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