i am working on a design which uses a stm32f427 device, and 3 external adc chips.
The ADC chips have 3 pins, SDO, SCK and CS.
The SDO,SCK wil be shared from the STM32F4 with all 3 chips, the 3 chip select signals will be managed independent by separate gpio port.
But i was wondering, i am quessing my SPI should be configured as SPI_Direction_1Line_Rx ?
When pooling down the selected CS device, this starts to send data
How is the generation of the clock SCK managed?