I'm working with the OTG FS core on the STM32F205ZE, and having some trouble understanding the sequences used in the example code. In the manual (RM0033) under register description for HCCHAR, the CHDIS/CHENA bits are marked "rs", meaning they can be read and set by the application, but only the USB core can clear them. However, in a number of places in the code, I see things like
USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
to halt a channel when the request queue is full, and
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg;
to start a channel transferring again after receiving a packet.
In my own code, I found that writing a 1 to CHENA (even though it's already set to 1) is indeed necessary to continue an IN bulk transfer after receiving the first packet. Given this, the manual's description cannot be complete. In section 29.17.4, under "Halting a channel", there is some description of a sequence of writes to CHDIS and CHENA, but it doesn't mention the step of clearing EPDIR as in the example code. I see there was some discussion a while ago, and a partial solution was posted, but it doesn't address how or why the various writes to CHDIS and CHENA work. In particular, there is mention of multiple 1 writes to CHENA scheduling multiple IN tokens, which doesn't appear anywhere in the documentation.
Some clarification from ST would be very helpful here.