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USART DMA IDLE State for STM32F401RETx

Question asked by Rashedul Islam on Nov 24, 2017
Latest reply on Nov 27, 2017 by Rashedul Islam

Hi All,

 

I was working on getting user input via keyboard over uart. The input could be varible length. To handle this issue I use HAL uart receive DMA (circualr mode). To get input and and tranfer it over uart, i got an example which actually serves my purpose fine. The example is by Akos Pasztor and link is given below:

GitHub - akospasztor/stm32-dma-uart: Efficient DMA timeout mechanism for peripheral DMA configured in circular mode demo… 

 

Now I implement my task in STM32L476RG Nucelo board and it was absolutely fine

In the example mentioned above, there is code block,

if((USART2->ISR & USART_ISR_IDLE) != RESET)
{
    USART2->ICR = UART_CLEAR_IDLEF;
    /* Start DMA timer */
    dma_uart_rx.timer = DMA_TIMEOUT_MS;
 }

Well, for my client project I got a board which has STM32F401RETx. But for the STM32F401RETx board I dont get defined the below:

USART2->ISR

USART2->ICR

USART_ISR_IDLE

UART_CLEAR_IDLEF

 

 

My question is why those above mentioned are not defined? and what is alternative for that ?

what modiftion needs to be done for the above mentioned code block? 

 

For STM32L476RG

the type is defined as belwo:

/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/

typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
__IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
uint16_t RESERVED2; /*!< Reserved, 0x12 */
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
__IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
uint16_t RESERVED3; /*!< Reserved, 0x1A */
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
__IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
uint16_t RESERVED4; /*!< Reserved, 0x26 */
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
uint16_t RESERVED5; /*!< Reserved, 0x2A */
} USART_TypeDef;

 

 

 

 

And for STM32F401RETx the type is defined as,

 

/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/

typedef struct
{
__IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
__IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
} USART_TypeDef;

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