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TIM1  6pwm how to disable - STM32F427

Question asked by anton.bogdan on Nov 22, 2017
Latest reply on Nov 22, 2017 by anton.bogdan



i have TIM1 generating 6 complementary PWMs and TIM2 set as encoder trigger from 3 hall sensors.  


TIM1 ticks at (1/50 000 000)  x 10000 =  5KHZ


After initialization of TIM1 without TIM2 being initialized, i have undesired toggle on the pwm outputs.


Isn't suppose TIM1 to set the pwms only when a hall event trigger is coming from TIM2? How to overcome this?


Please see the logic capture screen, where all OCx channels are on 

with  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1 

See the capture bellow


Another thing i have tried is to set TIM1 OCMode in  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing 

With this, i get the OCxN outputs active all the time,

See the logic capture bellow

And bellow is my timer1 initialization code

void init_pwm_timer(void){

NVIC_InitTypeDef NVIC_InitStructure;
TIM_TimeBaseStructure.TIM_Prescaler = 0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseStructure.TIM_Period = 10000;
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);


TIM_OCMode_Timing 000 - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).

TIM_OCMode_Active 001 - Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

TIM_OCMode_Inactive 010 - Set channel x to inactive level on match. OCxREF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

TIM_OCMode_Toggle 011 - Toggle - OCxREF toggles when TIMx_CNT=TIMx_CCR1.

TIM_OCMode_PWM1 110 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive.

TIM_OCMode_PWM2 111 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active.

TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1 ;//
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
TIM_OCInitStructure.TIM_Pulse = 2000; // 20 %duty
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;
TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Reset;
TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;

TIM_OC1Init(TIM1, &TIM_OCInitStructure);
TIM_OC2Init(TIM1, &TIM_OCInitStructure);
TIM_OC3Init(TIM1, &TIM_OCInitStructure);

TIM_OCInitStructure.TIM_Pulse = 1000;// 10%
TIM_OC4Init(TIM1, &TIM_OCInitStructure);

TIM_ARRPreloadConfig(TIM1, ENABLE);

TIM_OC1PreloadConfig(TIM1, TIM_OCPreload_Enable);
TIM_OC2PreloadConfig(TIM1, TIM_OCPreload_Enable);
TIM_OC3PreloadConfig(TIM1, TIM_OCPreload_Enable);

TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable;
TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable;
TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_OFF;
TIM_BDTRInitStructure.TIM_DeadTime = 7;
TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Enable;
TIM_BDTRInitStructure.TIM_Break = TIM_Break_Disable;
TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure);

CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
only when a commutation event (COM) occurs (COMG bit set or rising edge detected on
TRGI, depending on the CCUS bit).
Note: This bit acts only on channels that have a complementary output.
TIM_CCPreloadControl(TIM1, ENABLE);

When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit or when an rising edge occurs on TRGI
Note: This bit acts only on channels that have a complementary output.
TIM_SelectCOM(TIM1, ENABLE);// Register TIMx->CR2 -> set TIM_CR2_CCUS bit

TIM_SelectInputTrigger(TIM1, TIM_TS_ITR1);// TIMx->SMCR -> TS[6:4] = 001 HALL Timer2 is conected to input trigger of TIMER 1

NVIC_InitStructure.NVIC_IRQChannel = TIM1_TRG_COM_TIM11_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 7;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;

NVIC_InitStructure.NVIC_IRQChannel = TIM1_CC_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 7;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;

TIM_ClearITPendingBit(TIM1,TIM_IT_CC4); // Clear update interrupt bit

TIM_ITConfig(TIM1,TIM_IT_CC4 ,ENABLE); //Enable capture/compare interrupt on channel 4
TIM_ITConfig(TIM1,TIM_IT_CC1 ,ENABLE); //Enable capture/compare interrupt on channel 1

TIM_SelectOutputTrigger(TIM1, TIM_TRGOSource_OC4Ref);/* Master Mode selection */