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FIFO under run on  LTDC at 28 Mhz LCD clk

Question asked by Nikhil Narayanan on Nov 15, 2017

 Hi

We are using Tianma’s - TM070RVHG01  (800X480 resolution) TFT in our design with STM32F429 processor working at  168 MHz frequency. We are using EmWin Library on RTX operating system with LTDC support. We are statically storing the required ARGB8888 format in external SDRAM. The data is loaded from SDRAM to LTDC (STM32F4 LCD Controller) using DMA2D /FMC interface (Flexible Memory Controller – Working at 168/2 MHz).

 

The colour configuration is ARGB8888  and driver configuration of EmWin is GUI_LIN_32.

 

From datasheet (attached for reference) we understand that minimum DCLK is 28 MHz. So we are setting the DCLK as 28 MHz and calculated the parameters for LTDC which are as follows.

 

From Datasheet

HSYNC Width

20

VSYNC Width

3

HBP

46

VBP

23

Active Width

800

Active Height

480

BVBP

23

HFP

210

VFP

22

Calculated Value for LTDC Register

HSW

19

VSH

2

AHBP

65

AVBP

25

AAW

865

AAH

505

TOTAL W

1075

TOTAL H

527

Issue :

 

  1. We are find Tearing Effect in the display and the same time if we probe we could find FIFO underrun issue. Please let us know the above setting as correct for 28 MHz DCLK.
  2. When we reduce the DCLK to 24 MHz the display is stable but we are facing flicker issue. 

Queries :

Is there any solution for the above problems without using multi buffer support. Also could you send  sample source running on any RTOS for reference ?

 

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