Hi folks!

I'm working with a Netduino, which has an STM32F4, running at 168MHz.

I'm trying to do a calculation (specifically the following), which needs the ADC frequency (Fadc) and number of sampling periods (k):

I'm having a little trouble tracking these down, however.

Tackling Fadc first, it's set to default (0) in the firmware source, which is peripheral clock / 2 (according to the note next to it). I’m pretty sure from my reading that the peripheral clock is the same as the MCU clock, and my MCU is set to 168MHz. So 168MHz / 2 = 84MHz. However, the data sheet says that the ADC Clock Frequency (fADC) is between 30 and 36MHz for VDDA of 2.5V to 3.6V, and the VDDA on the Netduino should be around 3.3V. So what is the actual value here?

For the number of sampling periods, I found the following in source:

#define *STM32_AD_SAMPLE_TIME* 2 // sample time = 28 cycles

ADC1->SMPR1 = 0x00249249 * *STM32_AD_SAMPLE_TIME*;

So SMPR1 has a hex value of 0x00249249 which is 2,396,745 in base 10, so I get 4,793,490 for the number sampling periods, but that can't be right either, considering when I was looking at a sample for the STM32F1, it had a sampling time of 8:

With my answer 6 orders of magnitude off, I think it's probably not right. So I'd appreciate the help.

It's me again.

The ADC group has a programmable prescalar which you set to change the input clock to a value the ADCs can handle. See the ADCPRE field in the Reference Manual ADC_CCR register description.

The sample time register you are reading contains sample time bit fields for 9 or 10 channels. See the Reference Manual definition for the ADC_SMPR1 and ADC_SMPR2 registers.

Hal